FIG. 1 (prior art) depicts a plan view of an integrated circuit (IC) 100 illustrating a common power distribution scheme. IC 100 includes a number of blocks 105–109 adapted to perform various functions. Typical among myriad block types are transmitters, receivers, memory, and programmable logic. Blocks 105–109 communicate with one another via interconnect routing (not shown), and with external circuits via a number of input/output pads 110. Pads 110 provide physical connections to the external circuits and include circuitry that interfaces between the functional blocks and the external circuits and that protects IC 100 from electrostatic discharge.
Special power pads VDD and VSS deliver like-named supply voltages to a pair of power rings 115 and 120. (As with other designations herein, VDD and VSS refer to both signals and their corresponding nodes; whether a given designation refers to a signal or a node will be clear from the context.) Power branches 125 and 130 extend from respective power rings 115 and 120 to distribute power to blocks 105–109. Though not shown, a second power distribution network conveys power to the circuitry associated with pads 110. Power distributed to pads 110 is sometimes referred to as “dirty power” because the input and output circuitry draw relatively large amounts of supply current and thus introduce transient supply noise. ICs typically keep this dirty power separate from rings 115 and 120 to avoid injecting noise into blocks 105–109.
Power rings 115 and 120 and associated braches 125 and 130 exhibit impedance, so the respective local supply voltages Vdd and Vss at e.g. block 109 are somewhat lower than supply voltages VDD and VSS. The reduction in supply voltage is proportional to current and conductor length, so power-hungry circuits or circuits disposed in the center of an IC typically suffer greater supply-voltage degradation.
Many circuit parameters vary with supply voltage, so the reduced supply voltages Vdd and Vss impact circuit performance. For example, amplifier gain and the switching speeds of digital circuits drop with reductions in supply voltage. ICs can be designed to take these factors into account, for example by providing more metal lines and layers to deliver adequate power. These approaches are expensive, however, as the inclusion of additional metal increases complexity.
On-chip power distribution has long been an important issue in IC design. The problem is growing ever more severe with the improvements in device integration that flow from reduced feature sizes. One problem is that the resistance imposed by conductors increases with reductions in cross-sectional area, so smaller supply lines tend to drop more voltage. Another problem is that high performance circuits made with very small features require relatively low supply voltages, while the physical properties that dictate the operation of active devices place a lower limit on practical supply voltage levels. As supply voltages approach these low levels there is little “head room” left to allow for local supply-voltage reductions. These problems are particularly stubborn in high-speed systems because increasing switching speed increases the supply current, and increased supply current tends to reduce local supply voltages.
Delay variations that result from supply-voltage fluctuations are particularly problematic in systems in which the current drawn by neighboring blocks is subject to change. Referring to FIG. 1, for example, voltage levels Vdd and Vss to block 109 will vary depending upon the extent to which the remaining blocks 105–108 are drawing power, and are consequently loading power rings 115 and 120. The delays imposed by e.g. clock buffers within block 109 are thus subject to change with the activity in the remaining blocks. Such timing variations force IC designers to build in “guard bands” that account for worst-case timing variations; unfortunately, the inclusion of such guard bands limits device performance. There is therefore a need for methods and circuits that reduce or eliminate the impact of power-supply fluctuations on circuit performance.
Another problem that exists in the art relates to systems in which receivers are expected to receive data transmitted by one or more transmitters with disparate output characteristics. A receiver may be expected to receive data modulated using any one of a number of peak-to-peak voltage levels, for example. In such circumstances, the receivers may have insufficient gain for relatively low amplitude signals, or may exhibit more gain than is required for the higher amplitude signal. Insufficient gain can introduce receive errors, while excessive gain wastes power. There is therefore a need for calibration methods and circuits that optimize receivers based upon the characteristics of received signals.